It is well known in the art to provide radiation-hardening by design for dealing with single event upsets (SEU) in sequential elements and storage devices, such as flip-flops, SRAM (static random access memory) devices, etc.
In the case of combinational logic cells, data is not retained. Therefore, the risk in such cells is not of an SEU, but of an SET (single event transient). An SET is a voltage transient that occurs momentarily, and can cause errors if it occurs when the data signal propagated by a logic cell is being clocked.
Combinational logic cells generally form a major part of digital circuit design, and, for example, are used to implement clock trees, data paths, logical cones, etc. There is thus a desire in the art to provide a reliable radiation-hardening solution for such circuits. A difficulty, however, is that any solution that involves the addition of new logic cells is generally unsatisfactory, as these new logic cells may themselves be a source of SETs.
There is accordingly a need in the art to at least partially address one or more problems in the prior art.